S-SiCapTM Interposer IP
爱普运用DRAM制程工艺中内含电容的特性,提供内含S-SiCapTM Interposer方案。相较于DTC方案,爱普提供的S-SiCapTM Interposer 有较低的电容高度可以实现较薄的中介层厚度并减少TSV寄生电阻与电容值。
Key Features
- S-SiCapTM IP Cap. Density: 1200nF/mm^2
- Max. operation voltage: 1.5V
- Equivalent Serial Inductor (ESL): <0.2pH
- Equivalent Serial Resistance (ESR): 0.7Ω
- Insulation : >10GΩ